A memory arrangement can comprise a memory transistor for non-volatile storage of one bit.
Document DE 102004046793 B3 describes a non-volatile memory element that comprises two cross-coupled metal oxide semiconductor field-effect transistors, MOSFETs for short, each with a floating control electrode, “floating gate” in English.
Document U.S. Pat. No. 4,855,955 specifies a memory cell with two series-connected transistors that comprise two floating gate MOSFETs and a selection transistor.
A memory arrangement in which data are supplied simultaneously from two arrays to a read amplifier is shown in document U.S. Pat. No. 4,758,988.
Document US 2006/0092683 A1 describes a non-volatile memory with a block that comprises a first and a second sub-block, which are arranged in separate wells.
Documents U.S. Pat. No. 4,970,691, U.S. Pat. No. 6,765,825 B1 and U.S. Pat. No. 7,161,832 B2 show additional memory arrangements for non-volatile storage of a bit.